1. Field of the Invention
The present invention relates generally to the field of configuring modes of operation for integrated circuits and specifically to the selection of a clock multiplier for defining the internal clock frequency of a processor.
2. Art Background
The mode of operation for processors and other complex integrated circuits (ICs) is often defined by selecting among configuration options for various operating characteristics. For example, the internal clock speed for the Intel microprocessor architecture IntelDX4.TM. microprocessor manufactured by Intel Corporation of Santa Clara, Calif., is selectable between two times and three times the system clock speed. Some operating characteristics, such as the internal clock speed of the IC, typically must be defined before normal operation begins, while other operating characteristics may be defined after the start of normal operation.
A typical prior art method for selecting configuration options prior to normal operation requires the sensing of a voltage level, either logic high or logic low, on a dedicated or multiplexed input pin at some time during or after powering up the device. Typically, for binary logic, one input pin can only provide two configuration options. Three state logic may be used, but it is often very difficult to design with three state logic. In a binary logic design, if more configuration options are desired, more input pins, either dedicated or multiplexed, must be allocated. Allocating dedicated pins is undesirable because input pins are a limited and often scarce resource. Using multiplexed pins is undesirable because this method typically requires the use of a strapping resistor for each multiplexed input pin and because the number of available multiplexed pins is typically limited. Strapping resistors create DC paths, wasting system power, and using more strapping resistors results in greater power loss. This power loss is especially troublesome for battery-powered mobile personal computer systems such as laptop computers.
A typical prior art method for configuring a device after normal operation has begun uses software that selects the appropriate options by writing the correct information to one or more configuration registers. The primary disadvantage of this method is that it cannot be used to define operating characteristics that must be defined before normal operation of the integrated circuit can begin. Typically, software cannot be executed by a processor unless it is operating normally.
Neither of these prior art methods are appropriate when the goal is to define operating characteristics prior to the start of normal operation by selecting among three or more configuration options. The first method requires allocating more input pins, which may be difficult to do given the typical problem of having a lack of available input pins. The second method typically cannot be used until after normal operation begins. Therefore, a configuration selection circuit according to one embodiment of the present invention provides for the use of a single input pin for selecting between three or more configuration options. As will be described, an input configuration waveform is sampled at the input pin and compared to a plurality of known configuration waveforms. If a match is made, the configuration option corresponding to the matched configuration waveform is selected.